| 摘要 |
PURPOSE:To improve the degree of freedom of wiring and the element utility efficiency of the part under the wirings by forming a memory at the center of a chip when the memory is integrated in a master slice type semiconductor device and shortening a critical path. CONSTITUTION:A core 2 of KXK in size is disposed inside an I/O part 1 of a chip periphery, and composed of kXK element array 2 and a wiring region 22. A memory 3 of 2kX2k is formed at the center of the core. The wirings are formed only at x-axis or y-axis direction. When the memory 3 is disposed at the upper right of the core, the distance between the point B1 and A3 is 2K, and when disposed at the center of the core, the space between the point B1 and A3 is K/2+9/2Xk, becomes K/2+3/2Xk under pressure, and the critical path can be further shortened. When the memory 3 is disposed at the center, since the points A1B1-A4B4 are point symmetrical to the center of the memory, the degree of freedom of disposing and wirings of both the memory and the logic circuit can be increased. The element array of the core is symmetrical to the center before wiring, the degree of freedom of connecting an I/O 1 is large, the utility efficiency of the elements is increased, thereby increasing the integration. |
