| 摘要 |
PURPOSE:To determine whether read out data are to be utilized or data through an ECC circuit are to be utilized, and improve the processing speed of the titled error correction controlling system, by installing control bits which show presence or absence of a fixed trouble in a corresponding buffer storage into tag storages in a buffer memory. CONSTITUTION:C bits which indicate existence or nonexistence of a fixed trouble are added to each entry of a tag storage 2. The tag storage 2 and a buffer storage 4 are accessed in parallel and an address read out from the tag storage 2 is compared with a part of the remaining contents of an address register 1 at a comparator, and, when they coincide with each other, the read out data are treated as valid ones. When an error exists in the read out data, the rereading out is performed through an ECC circuit 7 and the error is checked whether it is a fixed trouble or not. When the error is a fixed trouble, the C bit is turned on and corrected data are obtained from the begining when the same address is read out thereafter. In this way, the access time can be shortened. |
