Logic regulation circuit for an electronic timepiece.

摘要

A logic regulation circuit for an electronic timepiece comprises first switch members (3a-3d), first memory circuits (5a-5d) for memorising data set by the first switch members, a second switch member (8), second memory circuits (10a,10b) for memorising data set by the second switch member, and a calculation circuit (11) for modifying the data in the first memory circuits in dependence upon the data in the second memory circuits and producing an output signal to set a desired frequency division ratio in a variable frequency divider.