发明名称 FREQUENCY CONTROL FOR PLL RECEIVER SYSTEMS
摘要 In a channel selection system of a television receiver set using a frequency synthesizer system, the local oscillator output of a voltage controlled oscillator in a tuner is coupled to through a prescaler to a programmable frequency divider. To a frequency division ratio specification input terminal of the programmable frequency divider is coupled a frequency division ratio setting data from a frequency division ratio memory. When the broadcast wave frequency is deviated from a predetermined value due to the frequency division ratio setting data, a fine tuning data corresponding to the deviation and a direction specification data representing the direction of the deviation are memorized in a random-access memory (RAM). The fine tuning data read out from the RAM is coupled to a fine tuning signal generator where it is added to or subtracted from the frequency division ratio setting data prevailing in the programmable frequency divider. The data obtained from the fine tuning signal generator as a result of the addition or subtraction is coupled as a new frequency division ratio setting data to a frequency division ratio specification input terminal of the programmable frequency divider.
申请公布号 GB2048002(B) 申请公布日期 1983.09.28
申请号 GB19800011943 申请日期 1980.04.10
申请人 TOKYO SHUBAURA DENKI KK 发明人
分类号 H03J7/28;H03J5/02;H03J7/02;H04B1/26;H04N5/00 主分类号 H03J7/28
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