发明名称 FEATURE NORMALIZING CIRCUIT
摘要 <p>PURPOSE:To realize a character recognizer with a high-speed and simple circuit constitution, by performing simultaneously both the counting and normalization with use of a fixed memory and an adder circuit. CONSTITUTION:The size of a character circumscribing frame of an input character pattern is set to a character width register 2 and a character height register 3. When a feature (i), where (i) is a feature number, is supplied to a feature input 1, the contents of an address (i) of a feature memory 6 and read out. The contents of the address (i) are added with the contents of an ROM which is designated for address by th registers 2 and 3 through an adder 5 and then written again into the memory 6. This process is repeated by times equivalent to countings of feature by giving a scan to a feature pattern register produced by extracting the feature. An integer part of the contents of the final address (i) of the memory 6 is equal to the result of normalization of the feature (i).</p>
申请公布号 JPS58163077(A) 申请公布日期 1983.09.27
申请号 JP19820044705 申请日期 1982.03.23
申请人 OKI DENKI KOGYO KK;NIPPON DENSHIN DENWA KOSHA 发明人 YAMASHITA YOSHIYUKI;KAWATANI TAKAHIKO
分类号 G06K9/46;G06K9/42;G06T3/40 主分类号 G06K9/46
代理机构 代理人
主权项
地址