发明名称 Method and apparatus for aligning an integrated circuit
摘要 A method and apparatus are disclosed for aligning an integrated circuit die (110) by use of a machine which directs a laser beam (32) downward on a wafer containing the die (110). Each die (110) is provided with one or more targets (52, 64, 78). A target (52) comprises an N+ region (56) within the target (52) and a layer of polysilicon (56) over an oxide layer (70). A laser beam (32) is scanned across the target (52) to detect a transition across an edge of a polysilicon layer (68). The transition is detected by the generation of charge carriers (36) within the region (34). The region (34) has an opposite conductivity type from that of the substrate (10) thus forming a PN junction. The PN junction is reversed biased by a voltage source (38) which is connected in series with a resistor (40) between the substrate (10) and the region (34). A center point is determined by calculating the midpoint between transitions. The establishment of a center of the target (52) establishes a reference point. The establishment of two such reference points determines a scaling factor and an angular orientation factor for the die (110) such that any other point on the die (110) can be accurately located.
申请公布号 US4406949(A) 申请公布日期 1983.09.27
申请号 US19810282858 申请日期 1981.07.13
申请人 MOSTEK CORPORATION 发明人 SPOHNHEIMER, JOHN V.
分类号 H01L23/544;(IPC1-7):G01B11/00 主分类号 H01L23/544
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