发明名称 Comparator circuit having hysteresis
摘要 A high-gain comparator circuit having an upper and lower input offset voltage associated therewith to establish hysteresis in response to a differential input signal supplied thereto. The output level state of the comparator circuit is caused to be switched from a first output level to a second output level in response to the differential input signal exceeding the upper offset voltage only after the hysteresis has been initiated whereby the comparator circuit is less susceptible to being caused to erroneously switch states due to noise transients. The comparator circuit comprises a differential amplifier adapted to receive the differential input signal for producing differential currents in first and second outputs thereof and includes first and second current mirror circuits coupled in parallel to the first and second differential outputs of the differential amplifier which produced the upper and lower input offset voltages in the comparator circuit when respectively activated.
申请公布号 US4406955(A) 申请公布日期 1983.09.27
申请号 US19810269250 申请日期 1981.06.01
申请人 MOTOROLA, INC. 发明人 LO CASCIO, JAMES J.
分类号 H03K3/2893;(IPC1-7):H03K5/15;H03K5/24 主分类号 H03K3/2893
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