| 摘要 |
A level shifter and latching circuit for watch consists of P type MOS transistor(Q1) which gate and source are connected sparately to digit signal selecting input(D) and segment signal input(S) and drain is connected to inverters(1,2) with a form of latch, a transistor (Q2) which gate is connceted to segment signal input(S) and source is connected to power source(VDD), and a transistor(Q3) which drain is connected to the Q1 and Q2 connected each other in series. The substrate tap of these transistors are connected in common to zero level power source(VDD) so that this system can operates as a level shifter and a latching circuit.
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