| 摘要 |
PURPOSE:To reduce the width dimension of wirings which form bit lines, by forming the bit lines in double layer structures via an insulation film. CONSTITUTION:An SiO2 film 52 for interelement isolation is formed in a P type Si substrate 51. The source region 53 and the drain region 54 of an MOS transistor are formed in divided regions. Word lines 56A and 56B constituted of poly Si are formed on the substrate 51 via SiO2 films 55. Further, the SiO2 film to insulate from bit lines 57A and 57B is formed also thereon. Through holes 102 taking connection to bit lines are formed on the region 54. Next, after forming insulation films 58, through holes 59 are formed, and bit lines 60A and 60B of the second layer are formed to the fixed patterns by evaporating Al. Thereafter, a cut aperture 61 is formed by cutting the part which unnecessitates connection. |
