发明名称 INSPECTING METHOD OF READ-ONLY MEMORY DEVICE
摘要 <p>PURPOSE:To detect a short circuit in wiring and double selection fault by using an array of alternate ''1'' and ''0'', or low and high levels as a dummy cell pattern for inspection and taking a test of functions. CONSTITUTION:As an arrangement of an inspecting cell, transistors and diodes are arranged alternately for, for example, a junction destructive type PROM. In other general ROM devices, memory cells are arranged so that pieces of information on a high and a low level are arrayed alternately. Thus, a short circuit in wiring and the double selection fault of a memory cell are detected.</p>
申请公布号 JPS58161199(A) 申请公布日期 1983.09.24
申请号 JP19820042690 申请日期 1982.03.19
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 OKUDA NORIYOSHI;MIZUE KATSUYA;OONO NOBUHIKO;UCHIDA AKIHISA
分类号 G11C17/00;G11C29/00;G11C29/02;G11C29/24 主分类号 G11C17/00
代理机构 代理人
主权项
地址