发明名称 FORMING METHOD FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain an IC having wirings of less floating capacity by opening a window at an MOS gate part, selectively etching and controlling the thickness of a gate oxidized film. CONSTITUTION:An active region and a field oxidized film are formed, and a gate oxidized film is formed on one surface. The gate oxidized films of the regions 21, 22 are etched, and the gate oxidized film is again formed on the entire surface. The thickness of the oxidized films of the gate M1, M2 become T11 at this time, and the thickness of the oxidized films of the gate M3 not opened by etching becomes T22>T11. Then, a polysilicon film 6, an SiO2 film 7, metal wirins 8, and surface protective film 8 are formed. The capacity per unit area of the polysilicon wirings on the field oxidized is film epsilon/T. The T22- T21 are selected to 30-50% of the thickness of the field oxidized film, and the capacity is reduced by 30-50% by increasing the T. The capacity is reduced for the metal wirings on the film 9.
申请公布号 JPS58158962(A) 申请公布日期 1983.09.21
申请号 JP19820040789 申请日期 1982.03.17
申请人 HITACHI SEISAKUSHO KK 发明人 NAKAMURA HIDEO;SAWASE TERUMI
分类号 H01L29/78;H01L21/822;H01L21/8246;H01L23/522;H01L27/04;H01L27/112 主分类号 H01L29/78
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