发明名称 MULTIPLEX PROCESSOR
摘要 PURPOSE:To provide the flexibility to an interruption process, by providing a communication means with which the interruption reception correspondence of receiver processors varies in response to the priority set to an interruption request given from the transmitter processor. CONSTITUTION:A processor B2 is started by a processor A1 through a starting part 31 of a processor B and then executes a process requested from the processor A1 through a processing part AB39. In case the processor B2 has a request of high priority to the processor A1, an interruption signal is turned on at an interruption signal producing part A310 to interrupt the processing. The processor A1 accepts the interruption given from the processor B2 at an interruption receiving part A33 and discontinues the execution of the system control (2) although the processor A1 is executing the control (2) through a processing part A32. Then the process requested from the processor B2 is executed at a processing part B34.
申请公布号 JPS58159172(A) 申请公布日期 1983.09.21
申请号 JP19820042261 申请日期 1982.03.17
申请人 FUJITSU KK 发明人 HIROTA YASUO;NODA TAKAHITO;SAKAI TOSHIHIRO;SASOU HIDEYUKI;BABA NOBUYUKI
分类号 G06F15/16;G06F9/46;G06F15/17;G06F15/177 主分类号 G06F15/16
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