发明名称 DATA PROCESSING SYSTEM
摘要 PURPOSE:To shorten the delay time, by dividing plural data processors into plural groups of different priorities, providing a bus use request line and a use permission line with each group and having a daisy chain system in each group. CONSTITUTION:Bus use request signal lines RQ0-RQ3 and bus use permission signal lines GR0-GR3 are connected to a bus controller 1. Plural data processors 2-n are divided into plural groups for each group of devices of equal priority. Then data processors 2-4 belonging to the same group are connected to the same line RQ3. For instance, a bus use request signal is delivered from the processor 3 via the line RQ3. When the controller 1 gives permission, a permission signal is delivered to the line GR3 in a daisy chain system and then transmitted to the requester processor 3 from the processor 2. The processor 3 occupies the bus. As a result, the delay time for the permission signal is shortened. Thus it is possible to provide an idle slot.
申请公布号 JPS58159126(A) 申请公布日期 1983.09.21
申请号 JP19820040828 申请日期 1982.03.17
申请人 NIPPON DENKI KK 发明人 ONODERA YUTAKA
分类号 G06F13/37;G06F13/36 主分类号 G06F13/37
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