发明名称 GENERATING SYSTEM OF SYNCHRONIZING CLOCK SIGNAL
摘要 PURPOSE:To obtain a synchronizing clock signal, by detecting an average value of a phase difference signal obtained by comparing an input TV signal with a signal which is obtained by frequency division of an oscillation output signal and controlling a variable phase shifter in accordance with this detection output to shift the phase of the oscillation output. CONSTITUTION:The phase difference between a horizontal synchronizing signal HD and a horizontal synchronizing signal, which is formed by counting down and frequency-dividing the pulse signal having a standard clock cycle of a crystal control oscillator 3 by a counter 2, is obtained, and a discrete value indicating its time difference is supplied to an averaging means 4 so that it is integrated for a proper time. An average value is obtained in the averaging means 4 for such time that the influence of a minute frequency fluctuation, etc. in a short time of the crystal oscillator 3 is eliminated, and a representative value of the phase difference is impressed to a phase shifter 5, and the phase of an oscillation output clock pulse signal from the oscillator 3 to the phase shifter 5 is shifted by a quantity corresponding to this phase difference, and a synchronizing clock signal CK synchronized with the input horizontal synchronizing signal HD with respect to phase is taken out.
申请公布号 JPS58159069(A) 申请公布日期 1983.09.21
申请号 JP19820040250 申请日期 1982.03.16
申请人 NIPPON HOSO KYOKAI 发明人 NINOMIYA YUUICHI;OOTSUKA YOSHIMICHI
分类号 H04N5/06;H04N5/067 主分类号 H04N5/06
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