| 摘要 |
PURPOSE:To reduce the circuit scale and to miniaturize the converting circuit of digital codes, by giving control to residue (m) bits among (n)-bit input of each selecting action of (m) units of selecting means. CONSTITUTION:Upper two bits i1 and i2 of a component expression input of 3 bits are supplied as addresses which are given to an ROM 2 and the delivered in the form of 3 bits. This 3-bit conversion output is supplied to a multplier 3, and the result of this multiplication is delivers in the form of an output of 3 bits. The selecting operation is controlled in response to the state of a lower bit i0 of the 3-bit input for a selector 4 which selects one of inputs and outputs of the multiplier 3. The 3-bit output of the selector 4 is converted into an output of a converting circuit. |
