发明名称 PHASE LOCKED OSCILLATOR
摘要 PURPOSE:To realize low power consumption, by providing a level holding circuit and a switching circuit, controlling their operations by a control signal, and keeping the frequency stability within a specified range. CONSTITUTION:When a control signal of terminals 16 and 17 is in a low level, the operation is executed as a regular phase locking circuit. When the control signal of the terminal 16 attains to a high level, a level holding circuit (LH) 11 outputs its immediately previous value continuously, subsequently, the control signal of the terminal 17 attains to a high level, and even if an electric power source of frequency dividers (DIV) 2, 5, a phase comparator (PD) 3 and an oscillator (OSC) 4 is cut off, a voltage control oscillator (VCD) sends out continuously a signal of the same frequency as before it is cut off. When the terminal 17 is released to a low level again, and subsequently, the control signal of the terminal 16 is released to a low level, the operation as the phase locking circuit is executed again, and the output frequency or phase of a voltage control oscillator 1 is controlled in accordance with the loop condition in that case.
申请公布号 JPS58159029(A) 申请公布日期 1983.09.21
申请号 JP19820042140 申请日期 1982.03.16
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 NISHIKI SADAYUKI;URABE SHIYUUJI
分类号 H03L7/18;H03L7/089;H03L7/14;H03L7/199 主分类号 H03L7/18
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