Quadrature tach decoder circuit.

摘要

A decoder for quadrature binary waveforms (A,B) comprises exclusive OR gates (14,24) for developing a clock signal at four times the rate of the input signals and a bistable latch (22) which responds to a signal indicating the phase sequence of the input signals. The latch is clocked by the clock signal. The indicating signal is developed by two stages of exclusive OR gates (14,16,20) including delay (18) for one input signal.