| 摘要 |
<p>PURPOSE:To suppress deterioration in writing characteristics, defective writing, and a decrease in reading speed, by inserting a load for level shifting into a common bus for a lead-in current and another lead-in current which flow to a row address buffer during data writing and reading respectively. CONSTITUTION:With regard to a memory cell type B-PROM having a fuse connected to the emitter of a bipolar transistor (TR), the resistance 41 is inserted into the common bus for a writing and a reading current between the output terminal of a row address buffer 11i and the input terminal (of a writing circuit in this case) of a row address decoder. Consequently, a decrease in hYE due to the current of a cell TR applied with a reverse bias between the emitter and base and an emitter-base breakdown of the cell TR is suppressed to suppress deterioration in writing characteristics and a decrease in reading speed.</p> |
