发明名称 MASTER SCLICE LARGE SCALE INTEGRATED CIRCUIT
摘要 PURPOSE:To contrive that the wiring design is remarkably facilitated, and the influence by characteristic changes generated from the difference of constitutions of input-output buffers is not given, by making the in and out relation between the first reference voltage wiring and the second one which should be connected to the input-output buffers equal. CONSTITUTION:In a chip 1, parts 3b, 3c, 3d and 3e provided by being connected to the connection part 3a of a source voltage VDD are monolithically connected each other and thus constitute the base part of source voltage wiring which forms an approximately rectangular form. In the periphery of the base part of source voltage wiring 3b, 3c, 3d and 3e, parts 4b, 4c, 4d, 4e' and 4e'' forming a monolithic constitution by being connected to the connection part 4a of an earth voltage GND are provided and show an approximately rectangular form as a whole, and accordingly constitute the base part of earth voltage wiring. The base part of source voltage wiring and the base part of earth voltage wiring are provided in parallel each other, and the input-output buffers 7 are provided by being connected to the both base parts. Therefore, the base part of source voltage wiring and the base part of earth voltage wiring are all in the relation of arrangement of the same in and out relation in each side part of the chip 1.
申请公布号 JPS58157155(A) 申请公布日期 1983.09.19
申请号 JP19820039347 申请日期 1982.03.15
申请人 RICOH KK 发明人 MIYAZAWA HIDEYUKI
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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