发明名称 PEAK HOLDING CIRCUIT FOR LENGTH MEASURING DEVICE
摘要 PURPOSE:To hold peak values surely and to prevent the decrease in responsiveness by operating a main counter only in the stage of updating the peak values and operating only the auxiliary counter in cases except said case. CONSTITUTION:While a main counter 18 is latched and holds the count value thereof, an auxiliary counter 48 keeps recording the length measuring value of an encoder 16 thereafter, and when the count value of the counter 48 resets to the value when a peak is detected, a zero detecting circuit 50 for the auxiliary counter detects the resetting and outputs a zero detection signal Z. The signal Z is converted to a latch releasing signal R with a reset circuit 52, and said signal resets the FF24 of a peak detecting circuit 22. Therefore, the circuit 22 resumes the latch releasing state and returns the main counter 18 to the ordinary latch releasing state, that is, to the countable state of the pulses from the encoder 16 with a latch circuit 40; thereafter, said counter starts counting the next up- length measuring signal A again. In this state, the counting of the counter 48 is stopped similarly to the initial state.
申请公布号 JPS58156801(A) 申请公布日期 1983.09.17
申请号 JP19820040455 申请日期 1982.03.15
申请人 MITSUTOYO SEISAKUSHO:KK 发明人 ARIAKE JIYUN
分类号 G01B7/00;G01B21/00;G01B21/10;G01D1/12 主分类号 G01B7/00
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