| 摘要 |
PURPOSE:To eliminate the inconvenience due to loss of time and a fixed number of transferred digits, by supplying a DMA end signal to a DMA controller from an input/output controller and applying the end interruption to an MPU through the DMA controller. CONSTITUTION:A circuit shown in the diagram is provided to a control circuit within a DMA controller. The contents of a transfer count register TCR are set at 0 when the DMA controller is carrying out the DMA transfer in response to the DMA request signal given from an input/output controller I/OC. As a result, the output of an AND gate 11 is set at H, and a DMA end signal is delivered to the I/OC. In this case, the outputs of a receiver 13 and an AND gate 12 are set at H. Then a D type FF14 is set with the rise timing, for example, of a detecting signal for end of DMA transfer. Thus the DMA is inhibited, and at the same time a DMA end interruption signal is supplied to an MPU to finish the DMA transfer. While the FF14 is set when the DMA transfer end signal is supplied from the I/OC. Thus the DMA transfer is over in the same way as mentioned above. |
