| 摘要 |
PURPOSE:To equalize the loads of memories and to improve the effect, by giving accesses with a bit deflection to an arbiter which connects plural devices to plural buses with no conflict as well as to the memories divided from plural buses. CONSTITUTION:The buses of plural processor units (not shown in the Figure) can be connected to and disconnected from common buses N1-N3 by means of matrix-shaped intersections, and each contact is controlled with no conflict by an arbiter (not shown in the Figure). Address converters 7-1-7-3 are provided to a memory 3 and then connected to the buses N1-N3 respectively. The outputs of the converters 7-1-7-3 are connected to buses L1-L3 via buffers 8-1-8-3 containing decoders 11-1-11-3. The memory part is divided into sections 6-1-6-k and has buses 9-1-9-k. These buses have matrix-shaped joints to the buses L1- L3, and each arbiter ABT1 control these joints. Each decoder D applies a bit deflection to disperse the deflection to each arbiter ABT1 in response to the quantity of load. This can equalize the loads among memory sections. |
