| 摘要 |
An associative memory cell includes a storage device having a pair of biasing nodes and a pair of output nodes, a plurality of access lines including a pair of BIT-lines and a TAG-line, and a plurality of gates controlling the accessing of the storage device by the access lines. The latter gates include a pair of sampling gates under the control of the BIT-lines and connecting the output nodes of the storage device to a pair of sampling nodes, and a pair of TAG-gates under the control of the sampling nodes and connecting the TAG-lines to one of the pair of the storage device biasing nodes. The described memory cell further includes READ-control and WRITE-control lines with the associated gates to perform the READ and WRITE functions. The pair of BIT-lines, the WRITE-control line and the READ-control line are all connected to the gate terminals of their respective gates, thereby making the device easier to drive, isolating the memory cell from the BIT-line buses, and improving reliability and speed.
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