| 摘要 |
A system for detecting the successful detection of a known serial data sequence of L bits. The system comprises clock pulse generating means for generating a train of clock pulses at a rate fc, shift register means having N stages each with an output terminal for serially receiving said data sequence at said clock pulse rate fc and for supplying the contents of each stage to the output terminal thereof, and memory means having at least M output terminals, N+M input terminals, and X memory locations each accessable by a predetermined address supplied to said input N+M terminals to supply the contents of said memory location to said M output terminals. Further provided is a latch having at least M input and output terminals and responsive to the signals on the M output terminals of said memory means to supply such signals back to the M input terminals of said memory means a time interval DELTA after the entering of a bit of said serial data sequence into said shift register means, where DELTA <1/fc. The contents of said memory locations are selected to advance through a first predetermined sequence of binary patterns when addressed by a second predetermined sequence of M+N addresses; The memory means is responsive to addresses formed by said first predetermined sequences of binary patterns and the coinciding data sequence contained in said shift register means to continue outputting said first predetermined sequence of binary patterns until said serial data sequence is completely received.
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