| 摘要 |
PURPOSE:To improve both the degree of integration and the yield, by sharing transistors of a differential pair to reduce two transistors down to one, and therefore, constituting a full system adder of a high working speed with a small number of transistors. CONSTITUTION:When input signals SG1, SG2 and SG3 are set to logic ''1'', the transistors TRQ1, Q3, Q4, Q6, Q9, Q10 and Q13 conduct respectively. While TRQ2, Q5, Q7, Q8, Q11, Q12 and Q14 are not conductive. In this case, the voltage at the collector of the TRQ12 is equal to the level of a voltage source VCC, and the carry output C is set a logic ''1''. The collector voltage of the TRQ10 is also equal to the level of the source VCC, and a sum output S is set to logic ''1''. |
