| 摘要 |
PURPOSE:To demodulate a signal of deteriorated characteristic accurately, by using the output of a delay circuit obtaining a digital signal delayed for a prescribed time as a threshold level input of a comparator. CONSTITUTION:An output of the comparator 2 is latched to the 1st D flip-flop (D-FF)4 with the leading of a synchronizing signal and latched to the 2nd D- FF 5 with the trailing. The output of the 2nd D-FF5 is the output of the comparator 2 delayed for one bit cell and this is given to the threshold level input of the comparator 2. That is, the threshold level of the comparator 2 is controlled with the level of the output data before one bit cell. Thus, the threshold level of the comparator 2 is set at each one bit cell to the input signal and the demodulated output is the demodulation of a substantial correct signal accurately. |
