| 摘要 |
PURPOSE:To design a system efficiency, by constituting a titled device so that a concurrence test, a maximum load test, and appreciation of system performance can be executed without connecting an actual DMA device to a DMA bus. CONSTITUTION:A DMA load varying device 10 is used by connecting it to a DMA bus 11, and optional information is set to a period setting part 34, a size setting part 38, a memory start address part 43 and a mode designating part 31, by which a request of the DMA bus, and its execution can be executed by an optional transfer period, an optional transfer area (DMA bus cycle) and an optional mode (read/write). Accordingly, a concurrence test of a DMA device 4, a maximum load test of the DMA bus 11 and appreciation of system performance can be executed without connecting one DMA device to the DMA bus 11, excepting the DMA load varying device 10. |
