| 摘要 |
PURPOSE:To increase gm and thus contrive the reduction into low noises, by shortening the gate length of a JFET, utilizing an Si3N4 film. CONSTITUTION:After an N epitaxial layer 2 on a P type Si substrate 1 is isolated by P<+> layers 3 resulting in the formation of N type source and drain 7 and 8, a window 11 of the size W2 is opened on an SiO2 film 4 and filled with the Si3N4 12. Next, an island-shaped Si3N4 layer 13 of W2>W1 is selectively formed, accordingly clearances 14 and 15 are formed, and it is etched by hot phosphoric acid into the formation of an island 16 of W3<W1. After oxidation, the Si3N4 layer 16 is removed by etching again with hot phosphoric acid. A P type gate layer 18 is formed by the thermal diffusion from the obtained window 17, and an Al wiring is performed resulting in completion. By this constitution, since the gate length of the JFET can be formed remarkably short, gm can be increased, and accordingly noises can be reduced. |
