| 摘要 |
PURPOSE:To improve the processing capacity, comparing with the case when a single bus is used, by placing a data group to be processed at the same time to devide it into different segments, and processing plural data simultaneously. CONSTITUTION:When bus switches 4-11, 4-21...4-3n are turned on, both buses connected to its bus switch are coupled. Turn-on and turn-off of each bus switch are controlled by an arbitor 5 for controlling an input/output bus, by a bus use request from processors 1-1, 1-2...1-n and the priority order decided in advance. Accordingly, as for the arbitor 5, the device 1-1...1-n are capble of using input/ output buses N1, N2 and N3 of a device 3 without competition. Also, a memory of the device 3 is divided into k-number of segments, and this divided memory segment is constituted so that it can be accessed independently from any one of optional buses N1, N2 and N3. |
