发明名称 SYSTEM FOR CHECKING MEMORY
摘要 PURPOSE:To judge the normality and abnormality of a memory having plural memory elements arranged in a matrix-like configuration, by making an arrangement that the memory is dividing into several groups and checking at every group to complete checking even of a memory having a large capacity in a short time. CONSTITUTION:The output of an FF group 5 is made effective by controlling an FF8 and data are written in an FF corresponding to a designated memory group, and then, data are simultaneously written in and read from memory elements 11-48 in parallel. Try-state gates 3-1-3-8 are controlled by a read signal outputted as the result of AND and the output of AND gates 2-1-2-8 obtained by AND operation are read out to a data bus as data to be inspected. Moreover, try-state gates 4-1-4-8 are controlled by a read signal outputted as the result of OR and the output of OR gates subjected to OR operation are read out. Then data to be inspected are judged by comparing them with expected value data.
申请公布号 JPS58150198(A) 申请公布日期 1983.09.06
申请号 JP19820033550 申请日期 1982.03.03
申请人 USAC DENSHI KOGYO KK 发明人 WAKABAYASHI MASARU;TERANISHI MASAHIRO
分类号 G06F12/16;G11C29/08 主分类号 G06F12/16
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