| 摘要 |
PURPOSE:To improve the processing speed of the vector operation, by executing the parallel vector processing and the common vector processing in individual private devices, and accessing simultaneously vector registers by systems suitable for respective processings. CONSTITUTION:A vector register device 11 is provided with independent vector registers VR0-VR3, and each VR includes numbered element data 0-7. A vector processing device 6 takes all data of the device 11 as the object to perform common processings such as data load from a main memory 5 to the device 11, data store from the device 11 to the memory 5, and shifting of element data to an optional address position of the device 11. Four element data having the same number are allocated to logical operation devices 13-0-13-7; and when an optional VR is selected by a selecting circuit 14, they are connected to cells having element numbers corresponding to this VR, and operation processings of devices 13-0-13-7 are executed simultaneously in parallel by the control of a controller 12. |
