| 摘要 |
PURPOSE:To improve a processing speed as the whole, by making times required for the read of microinstructions, the read of operation data, and the write of operation results uniform approximately, and assigning 3 microcycles to one microinstruction. CONSTITUTION:When an instruction word from a main storage device 11 is read out to a microprogram muPG storage controller 12, a corresponding PG is read out from an ROM 13 and is stored temporarily in a mu instruction register 32. Data read out from a general register 14 to an X bus 17 and a Y bus 18 on a basis of data in fields RX and RY of the register 32 are operated in an operating device 15. Data from a field RZ is latched in a write latch 33 and is decoded in a decoder 36 to become a write control signal to the register 14. The operation result of the device 15 is delayed in a destination latch 38 by a time corresponding to one mu cycle and is stored in the register 14 through a Z bus 19. Consequently, the processing of one mu instruction is divided to 3 cycles, namely, the read of the mu instruction, read and operation of operation data, and the write of the operation result, and they are processed in parallel. |
