| 摘要 |
PURPOSE:To prevent system-down, by providing a counter circuit for the 1st and the 2nd shift registers connected to a microcomputer of a failure detector, using an odd number parity in addresses and control data, and detecting a failure automatically. CONSTITUTION:The address and control data of each terminal 6 are formed at the microcomputer 2 in response to the input from a key input display circuit 1 and supplied to a shift register circuit 3 with the data request of a waveform producing circuit 4. The circuit 3 cosists of the 1st and the 2nd shift registers, the input side of the 1st register is grounded and ''0'' in the data from the circuit 3 is counted at a counter circuit 10. ''0'' is inputted to the input of the 1st register at each clock, and the data is brought to zero as far as the address and control data are not set again after the 16th clock. The odd number parity is provided for the 16-bit of the address and control data, the parity is used for the failure detection to reset the entire system initially. |
