| 摘要 |
PURPOSE:To speed up error corrections by providing a latch circuit for correcting polynomial data, and finding and storing correcting polynomials corresponding to the data lengths of many kinds of abbreviated data differing in data length in the latch circuit. CONSTITUTION:Input data d1 is processed by division mod 2 using a generating polynomial and a check bit pattern which is the remainder is added behind the input data d1 to output transfer data d2. This data d2 is written on a memory such as a magnetic disk, etc. Then, the input data d2 including the check bit pattern is inputted from the memory 2 to an ECC circuit 3 and also supplied to a data buffer circuit 5 at the same time. To prevent the waste of time when unnecessary data is sent out during an error correction, the correcting polynomial is found previously and stored in the latch circuit. Thus, the division mod 2 using the generating polynomial and multiplication using the correcting polynomial regarding the input data d2 are carried out at the same time. |
