| 摘要 |
PURPOSE:To obtain an operated result having required accuracy, by preparing an accelerating factor, speeding up the convergence of numerals and executing weighting operation of the first several items. CONSTITUTION:A V counter 52 is cleared to ''0'' by a reset signal RS4 from a controlling device 38, the contents of a shift signal generating circuit 50 is set up to D/2V<+1>=10/2<1>=5 and binary display values ''1'' are outputted from a shift register 49 and supplied to a selective matrix circuit 48. Outputs corresponding to required divisions in a division table 7 are supplied to a comparator 53. The output of a q register 45 is applied to the comparator 53 and an output from the comparator 53 is supplied to an AND gate 56 to open the AND gate 56. Since the contents of the shift register 49 is supplied to an encoder 57, an output indicating a0=5 e.g. is obtained from the encoder 57 and an output SL is obtained from a comparator 58 because a0=5<D-1=10-1=9. |
