发明名称 SOLDERING METHOD FOR FLAT PACKAGE IC
摘要 <p>PURPOSE:To make automatic operation easy and to improve reliability by enabling soldering a pattern by such a method as previous dip soldering, by soldering an IC by the reference of the height of a dip solder and by releasing the elasticity of a lead leg after the soldering. CONSTITUTION:Soldering is carried out by the reference of a dip solder 16. The reference of the height for soldering an IC 10 is made nearly equal to the height of the dip solder 16 and lead legs 13, 14 are so adjusted as to the quantity of absorbing the dispersion of the lead legs 13, 14 and the dispersion of the dimension in the direction of the height of the dip solder 16. Consequently, the soldering is made possible by making no change of the height of the IC 10 after the soldering and by forming wedge like solder fillets 21, 22 between the lead legs 13, 14 and a conductive pattern 15. After the soldering, no stress remains and reliability is further increased since elasticity can be released by the adjustment of the lead legs 13, 14.</p>
申请公布号 JPS62247552(A) 申请公布日期 1987.10.28
申请号 JP19860090816 申请日期 1986.04.18
申请人 SONY CORP 发明人 KAWATANI NORIO
分类号 H01L23/32;B23K1/00;H05K3/34 主分类号 H01L23/32
代理机构 代理人
主权项
地址