发明名称 ARITHMETIC UNIT OF VECTOR
摘要 PURPOSE:To reduce the time required fo the setting of the initial information and to improve the execution efficiency of an operator, by setting up the address, address increment and vector length for the preparation of the succeeding vector operation in backup registers. CONSTITUTION:Registers 210-212, 220-222, 230 are added as backup registers in accordance with address registers 110-112, address increment registers 120- 122 and a vector length register 130 respectively. In vector operation, the addresses of respective vectors, the address increment and the vector length are stored in the backup registers 210-212, 220-222 and 230 respectively. These values are transferred to the registers 110-112, 120-122, 130 respectively to execute the vector operation. During the execution of vector operation, these backup registers are initialized for the succeeding vector.
申请公布号 JPS58146968(A) 申请公布日期 1983.09.01
申请号 JP19820028904 申请日期 1982.02.26
申请人 TOKYO SHIBAURA DENKI KK 发明人 MAEDA AKIRA
分类号 G06F17/16;G06F15/78;(IPC1-7):06F15/347 主分类号 G06F17/16
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