发明名称 MEMORY ACCESS CONTROLLER
摘要 PURPOSE:To improve the throughput of a system by providing a means which decides identification information, and executing low-speed processing commands in the order of acceptance to a command stack and high-speed commands while by-passing the command stack. CONSTITUTION:The decision means 7 decides whether or not the high-speed processing identification bit of a command inputted to an input register 2 is significant, so that whether the command is a high-speed command or low-speed processing command is decided. The low-speed processing command is inputted to the input command stack 4 where it is stored on a first-in first-out basis and processed in the order of acceptance and the processing result is stored in an output command stack 5 so as to wait for the ready signal for the use of a common bus line 1 and then sent out to a processing requesting device 22 in the order of storage. The high-speed processing command, on the other hand, is executed speedily through the by-pass means 6b of the input command stack without being inputted to the input command stack 4, and the execution result by-passes the output command stack 5 through output-side by-pass means 3b and 16b.
申请公布号 JPS62245462(A) 申请公布日期 1987.10.26
申请号 JP19860090359 申请日期 1986.04.18
申请人 FUJITSU LTD 发明人 KAWANISHI KIYOSHI
分类号 G06F12/00;G06F13/16;G06F13/18 主分类号 G06F12/00
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