发明名称 SISTEMA DE PROCESSAMENTO DE ERRO DE ARMAZENAMENTO DE CHAVE
摘要 A key storage error processing system works with a key storage having stored therein main storage keys (K) respectively corresponding to pages (P) into which a main storage (MS) is split. Each key (K) has a reference bit (R) relating to page access and a change bit (C) relating to page updating. Respective parity bits are associated in the key (K) with the reference bit (R) and the change bit (C), to form bit pairs. Detecting means are provided to detect parity error in a bit pair of a read out key (K). In the event of such an error the reference bit (R), or change bit (C), is set to "1", to indicate page access or page updating has taken place, and the relevant parity bit is set to "0". Thereafter the key (K) is rewritten.
申请公布号 BR8205588(A) 申请公布日期 1983.08.30
申请号 BR19828205588 申请日期 1982.09.23
申请人 FUJITSU LIMITED 发明人 TERUTAKA TATEISHI;KAZUYUKI SHIMIZU
分类号 G06F3/00;G06F11/10;G06F12/10;G06F12/12;G06F12/14;(IPC1-7):G06F11/10 主分类号 G06F3/00
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