发明名称 DECODER
摘要 PURPOSE:To reduce the noise to a reproduced speech due to a mistake and to simplify a circuit constitution, by stopping the supply of latch clock at the detection of parity error, and interruputing data rewrite of latch. CONSTITUTION:An AND gate 11 passes through a latch clock as it is, an AND gate 12 inverts the latch clock and tives it to latches 1 and 2. The latches 1, 2 latch a PCM data, the data is applied with D/A-conversion 3 and applied to a speech output circuit via an LPF4 and a buffer 5. When an error is detected at a parity check circuit 5, the output closes the gate 11, blocks the supply of the latch clock to the latches 1, 2, and the preceding data is kept as it is without being rewritten for the latches 1, 2.
申请公布号 JPS58145251(A) 申请公布日期 1983.08.30
申请号 JP19820029363 申请日期 1982.02.23
申请人 MATSUSHITA DENKI SANGYO KK 发明人 TAIRA HIDEKAZU
分类号 H04B14/04;(IPC1-7):04B12/02 主分类号 H04B14/04
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