| 摘要 |
PURPOSE:To decrease the chip size, by using a variable SCF operated at clock frequencies fs and fs/M and realizing high and low cut-off frequencies respectively. CONSTITUTION:A variable SCF1, H1(Z) of transfer function and a variable SCF2, H2(ZM) of transfer function are connected in cascade. The SCFs 1, 2 are LPFs operated in frequencies fs and fs/M(where; M is a positive integer). In realizing fc1-fc3, the cut-off frequency of the SCF1 is fixed to fc6 and the cut- off frequency of the SCF2 is made variable. Then, in realizing fc4-fc6, a switch 3 is turned on, the SCF2 is bypassd and the SCF1 is exclusively used. Thus, the number of unit capacitors is reduced and the chip size as an integrated circuit is reduced accordingly. |
