发明名称 SHARED MEMORY CONTROLLER
摘要 PURPOSE:To avoid the breakdown of all systems, by breaking the power supply to one data processing system out of data processing systems consisting of plural data processors. CONSTITUTION:A foreshowing signal 10 for a power break is sent from a power source 2 to an FLUG 3 in a data processor 1 to set or reset the FLUG, and the address of a CONTROL STAGE 5 is controlled by a microprogram sequencer 4 and is sent to a data processing part 6. When the power supply is broken, the previous notice of the power break is displayed, and the power supply is broken after the elapse of a certain time. In this case, the time from the previous notice to the power break is made longer than the time from LOCK to LOCK release, and troubles due to the power break during this time are avoided.
申请公布号 JPS58144958(A) 申请公布日期 1983.08.29
申请号 JP19820027338 申请日期 1982.02.24
申请人 HITACHI SEISAKUSHO KK 发明人 SUZUMURA SHINYA;TAKAMATSU RIYOUICHI;MORIOKA TAKAYUKI
分类号 G06F11/00;G06F12/16;G06F15/16;G06F15/177 主分类号 G06F11/00
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