| 摘要 |
PURPOSE:To simplify and speed up calculation processing by making the horizontal and vertical registers attached to a register group always keep their maximum values and preventing the generation of an extremely non-linear corresponding passage to fine the optimum corresponding passage. CONSTITUTION:Respective parameters ai, bj (i, j=1-8) stored in a reference pattern memory 1 and an input pattern memory 2 are inputted to an error detecting circuit 3 through switches Fi, Gj respectively and an error d (ai, bj) is calculated in the circuit 3. From a center register RG41 to store error integrated values corresponding to the combintaion coordinates i=j=n (n=1-8) of both the parameters, horizontal registers RG42-44 corresponding to the combination coordinates of n-1-n-3 and n and vertical register RG45-47 corresponding to the combination coordinates of n and n-1-n-3, three values are inputted to a minimum value detecting circuit 5 to select the minimum value. The error from the circuit 5 is added to the error (d) from the circuit 3 by an adder 6 to obtain the minimum error integrated value. The contents of the RG41-46 excluding RG44, 47 always keeping their maximum values infinity are rewritten by the minimum error integrated value. |
