| 摘要 |
A pulse code modulated signal is retimed in a regenerator using a decision circuit supplied by a clock and is demultiplexed. The clock frequency is derived from the data stream using a phase locked loop clock extractor. The phase detector comprises first, second and third pairs of transistors, the collectors of the transistors (70, 72) of the first pair being connected to the common connected transistors (74, 76 and 78, 80) of second and third pairs. A first delay circuit (82) is connected between one of the first pair of transistors and one transistor (74, 80) of each of the second and thrid pairs of transistors. A second delay circuit (84) is connected between the other of the first pair of transistors and the other transistor (76, 78) of each of the second and third pairs of transistors. VCO and VCO signals are applied to respective base electrodes of the transistors of the first pair and the current pulses are applied to their emitters. |
