| 摘要 |
An interval timer circuit (similar to a relaxation oscillator) including a single comparator having first and second inputs thereto and an output therefrom. The circuit includes a first circuit leg having an R-C circuit with a control point therebetween, with said control point being connected to the second input of the comparator. A first reference voltage is established at the first input of the comparator whereby its output changes from a second state to a first state when an increasing or charging voltage at the control point exceeds the first reference voltage. A second circuit leg establishes a second reference voltage at the first input of the comparator in response to the first state at the output thereof. A third circuit leg or discharging circuit produces a decreasing voltage at the control point in response to the first state and when the decreasing voltage at the control point is less than the second reference voltage, the output of the comparator changes to its second state to repeat the process. |
