| 摘要 |
PURPOSE:To obtain a linear circuit of high dielectric strength and an I<2>L of high integration degree on one chip, by a method wherein one of two insular regions separated from each other by a thick oxide film is further separated by means of a shallow oxide film. CONSTITUTION:A multilayer mask constituted by an SiO2 layer 4 and an Si3N4 layer 5 is provided on an N<-> epitaxial layer 3 on a P<-> type Si substrate having an N<+> layer 2 selectively buried therein, and an I<2>L-forming region is covered with a resist mask 6 to perform an etching as at 7. By utilizing eaves of the mask 5, B ions are implanted into only the center of the recess 7 to form SiO2 layers 8a, 8b and the layer 8b and the N<+> buried layer 2 are brought into contact with each other. In this case, the layer 8a is deeper than the layer 8b, and P<+> channel stoppers 9a, 9b are also formed. Thereafter, the Si3N4 5 is removed, and a P<+> base 10 and an N<+> emitter 11 are provided to form an npn element. On the other hand, a P base 12, an N<+> collector 13 and an N<+> emitter 14 are provided on the I<2>L side to form an inverted npn element. By this constitution, both the I<2>L and the linear circuit portion are separated by means of the oxide films. Accordingly, the linear circuit can have a high dielectric strength, and the I<2>L has a walled emitter structure and therefore can be greatly increased in integration degree, so that the chip can be reduced in size. |
