发明名称 DATA TRANSFER CONTROLLING SYSTEM
摘要 PURPOSE:To attain high-speed data chaining, by reading out the next storage address before the end of data transfer, reading out it at the end of the transfer and comparing a channel command word read out before with a command word. CONSTITUTION:A byte count controlling section 7 reads out the next channel command word (CCW) from a main storage devce 1, prior to the end of data transfer of the present CCW via a memory interface control section 3. The count value is subtracted by one at each end of data transfer and when the value reaches 0, the next CCW is read out from the device 1 again and compared with the CCW read out before. When the values are coincident, the data transfer is preformed normally. When dissident, the next CCW is rewritten with the write data to the final device 1 of the present CCW. Simultaneously, a CCW dissident signal 19 is given to an IO interface controlling section 4 from a comparator 9 and the data transfer with the IO device during execution at present is interrupted.
申请公布号 JPS58142420(A) 申请公布日期 1983.08.24
申请号 JP19820024372 申请日期 1982.02.19
申请人 HITACHI SEISAKUSHO KK 发明人 OKUDA HIRONARI;OGAWA TETSUJI;MORIKAWA TAKASHI
分类号 G06F13/12 主分类号 G06F13/12
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