Digital signal processor.

摘要

A digital signal processor has timing means (5, 8) for providing a succession of sample intervals (ut) in which an incoming digital signals may have discrete values (e(o)). A serial delay (40, 52) such as a multi or single bit shift register progressively delays a digital signal giving a delayed signal (e(m)). An arithmetic section (36) has a plurality of elements (41, 54) such as multi or single bit multipliers, or difference squares. Each element operates on non delayed signals (e(o)) and signals (e(m)) from an associated stage of the delay (40, 52). An accumulating store (37) has a plurality of channels (45, 57) each associated with an arithmetic element (41, 54). Collectively the channels (45, 57) provide the required mathematical operation, auto or cross correlation function or structure function calculation. The interval of delay between channels (45, 57) is arranged to increase substantially geometrically e.g. by V2. The overall delay increase may be variable and geometric although increases between adjacent channels (45, 57) may be approximations to a geometric increase. A variable clip level circuit (53) may be incorporated into the input to the serial delay (52). In one configuration the delay intervals may be adjusted to be the same between each channel.