发明名称 |
Data processor control subsystem |
摘要 |
An improved data processor control subsystem in which a cycle counter having a plurality of cascade-connected stages also comprises one or more supplemental or dummy stages, which can be selectively inserted or removed from the chain of cascade-connected stages, to alter the number of sub-cycles in an operating cycle, thereby decreasing the complexity of associated decoding circuitry.
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申请公布号 |
US4400776(A) |
申请公布日期 |
1983.08.23 |
申请号 |
US19800186883 |
申请日期 |
1980.09.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BAZLEN, DIETER;BOCK, DIETRICH W.;GETZLAFF, KLAUS J.;HAJDU, JOHANN;PAINKE, HELMUT |
分类号 |
G06F1/04;G06F9/22;G06F9/26;G06F9/30;G06F9/302;G06F9/38;(IPC1-7):G06F9/00 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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