发明名称 PROGRAMMABLE LOGIC CONTROLLER
摘要 PURPOSE:To increase the arithmetic speed and at the same time to eliminate a memory which stores the intermediate arithmetic result, by executing plural logical operations in parallel and at one time. CONSTITUTION:A CPU1 fetches the data of a digital input device 3 on the basis of a programmed instruction and then delivers the result of operation to a digital output device 4. In this case, the program is stored in a program memory 21, and the contents of the memory 21 are transferred to a parallel arithmetic part 24 by a command of a control part 22. On the other hand, the contents of the device 3 are transferred to an input buffer register 23 via a data bus 14. An arithmetic logical equation is decided at the part 24 with the information transferred from the memory 21. Then a parallel operation is given to the contents of the register 23, and at the same time the contents of the register 23 are fed to the device 4 via the bus 14.
申请公布号 JPS58140849(A) 申请公布日期 1983.08.20
申请号 JP19820022673 申请日期 1982.02.17
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAOKA HIROMASA
分类号 G06F9/38;G05B19/048;G05B19/05;G06F7/00 主分类号 G06F9/38
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